In the last post we created a cost model of the SoC design process, modeling development stages separately and composing them for the overall design flow. Each stage models a few basic components: baseline development work, iterations (e.g., debug loop), hand-offs to and from other stages, and bug reporting.
This post will discuss use of a single-stage model, a multi-stage model, and implementation details, providing examples from RTL and verification stages.
Continue reading “SoC design cost model usage and implementation”
“How much is verification going to cost?”
The last post started with this simple question and looked at empirical studies on the cost of bugs. This time we will approach it from the opposite direction and create a cost model for the System-on-Chip development process, including the cost of bugs.
A cost model parameterized with a project’s data is more than a theoretical framework – it is a management tool to perform methodology and tool tradeoffs, identifies opportunities for improvements, and aligns with efficiency metrics as described in the Project Metrics post.
Continue reading “Building a Cost Model for an SoC Design Flow”
It all started with a simple question: “How much is verification going to cost?”
This is an important question since verification is a major part of System-on-Chip development efforts – 56% according to a recent study (the 2012 Wilson Research Group study sponsored by Mentor Graphics). The same study shows that verification engineers spend 35% of their time in debug.
Understanding the cost of bugs seems like a good place to start looking for answers.
Continue reading “The cost of bugs”